TDCs as VME slaves – VME multiblock read

	Ex. 20 TDCs in a crate

Setup:
- program all TDCs to respond to a common alternate address range 
used only for multiblock transfers.  Only the TDC having the token 
will actually respond to the address cycle.

- when initialized, TDC #1 has token

- program TDCs #1-19 to pass token when they have transferred 100   
events.

- program TDC #20 to issue a BERR (bus error) when it has 
transferred 100 events.

- program TDC #1 to interrupt crate controller when 100 or more 
events are in its buffer.

Operation:

- TDC buffers fill in parallel, TDC #1 interrupts controller when 100 
events in buffer.

- controller starts block read from common address range, causing 
TDC #1 to respond because it has the token.

- when 100 events have been extracted token is passed to TDC #2 on 
Iackin-Iackout daisy chain line.

- Events continue to be extracted from TDCs #2-19 in this way.  
They appear to the master as a single logical slave.  When re-
addressing occurs (after maximum number of bytes for a single 
block transfer has occurred), the TDC having the token will 
respond. 

- TDC #20 drives BERR (bus error) when he has transferred 100 
events.   BERR terminates the block read and resets the token to 
TDC #1.

TDC Data FIFO

4 Mbyte of RAM is organized as a circular buffer.  Address pointers 
(counters) tell where to write data to or read data from.  Although 
constructed from RAM, individual locations will not be addressable from 
VME.  Thus, in principle, we only need a single VME address to access the 
data.  

However, some VME CPUs don’t handle FIFOs properly during block 
transfers.  For example, after transferring 256 bytes of a BLT cycle (32 bits) 
the master will automatically increment the address by 256.   The master 
assumes it is accessing RAM.

To be compatible with such masters we must define a 4 Mbyte range of 
address for the data FIFO.  A read from any address in this range will simply 
yield the next valid data word.




Registers


(1) Control/Status registers for F1 TDC chips.

(2) Control/Status registers for FIFO operation.
- number of events in a ‘block’ (same for all boards in a set)
- set interrupt options, interrupt ID (only 1st board can interrupt)
- current total word count
- error flags (e.g. FIFO full on write, FIFO empty on read)
- token passing parameters: enable, first board, last board, start 
common address, end common address, address access mode

(3) Event Block Word Count
- number of words for the current block of events. The count for 
each block of events is stored in a special FIFO.

(4) Data
- 4 Mbytes of address space




Common Address Range for Multiblock Read

- The range must be at least 4 MBytes x Number of boards in the set

One implementation:
Design to allow the 4 MByte FIFO address ranges of the boards to be 
placed adjacent in VME address space.  A contiguous address range for the 
entire board set results.  Standard VME cycles will access this address range 
in ‘non-privileged’ mode.  The Multiblock protocol will result when this 
address range is accessed in ‘supervisory’ mode.