ADC Design

A majority of the detector channels will require energy and/or low resolution ( 1 ns) time measurements. By instrumenting these channels with high speed (250 $\,$MHz ) flash ADCs, one can pipeline the energy information and provide enough sampling for course timing measurements. The primary drawback to such a design is that a large amount of data can be generated (e.g. 1 $\mu$s at 250 $\,$MHz and 8 bits/sample gives 250 bytes/channel). This data must be ``processed down'' at the front-end to give more specific energy and time information.

Appropriate commercial designs are not currently available; hence, we propose to build a flash ADC prototype board in a VME form-factor. A possible solution would be to use the Analog Devices 9054 (200 $\,$MHz 8 bit) flash ADC chip interfaced to two Cypress 100 $\,$MHz dual-ported RAMs. Prompt energy information would be needed for the Level 1 trigger, so prior to storage in the DP-ram the FADC data would be passed through a series of shift registers and sampled and summed over a specified time window. Upon reciept of a Level 1 trigger a section of data from the DP-Ram would be read and processed, and the reduced data would be stored in a FIFO available for readout from the VME side. A possible solution for the processor and FIFO interface would be the Xilinx Vertex FPGA (100 $\,$MHz ).