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TDC Design

The F1-TDC chip is a new, high resolution Time-to-Digital Converter that has been specifically developed for the COMPASS [2] experiment at CERN and implemented in 0.6 micron CMOS technology. It has been designed to address time measurements on a variety of detectors using a pipelined architecture and as such can be operated deadtimeless in high resolution (4 channels with 60 ps/LSB each), low resolution (8 channels with 120 ps/LSB each) and latch (32 channels with 5.7 ns/LSB each) modes. It is being marketed by acam [3] for under $60 in quantities of 2000 units.

The core of the F1-TDC is composed of a 19-tap, asymmetric ring oscillator, Phase Locked Loop (PLL) capable of operating at an input reference clock frequency of up to 40 $\,$MHz and achieving a 16-bit dynamic range. Time measurements can be referenced to a Synch-Reset input, to a Common Start input or to a Trigger input. Each channel has dual port, 16 hit buffers, a trigger matching buffer and 8 readout buffers. The trigger matching feature of the F1-TDC, with programmable trigger latency and programmable hit selection window, is of critical importance to pipelined DAQ architectures. Valid data for all channels is stored in a 16-register, 24-bit interface FIFO from which data can be retrieved at a databus readout rate of up to 50 $\,$MHz or in burst mode.

We expect to start the design of a multi-channel TDC prototype at Jefferson Lab in the very near future. This prototype will incorporate F1-TDC chips, readout and setup data storage, a processor and VME interface.


next up previous
Next: Clock Distribution/Trigger Syncronization Up: Hall D Hardware requirements Previous: ADC Design
David Abbott
1/5/2000