A synchronous pipelined data acquisition system operating at 250 
MHz has
been proposed for Hall D. Here we explore the possible solutions for
distributing and synchronizing this clock. We assume in this study a
board + crate architecture for the front-end electronics.
The goals are twofold: all channel pipelines of the system should be clocked at the same time, and all the pipelines of the system should all be enabled for clocking on the same clock interval. Accomplishing these allows the 4 ns detector data samples to be correlated across the entire system. Achieving a channel clocking skew of less than 1 ns across the entire system is our goal.
There are two signals we consider: clock and reset. Each front-end board has a counter that is incremented by clock. The count is held at zero while reset is asserted; counting is enabled when reset is deasserted. The count value serves to time stamp the data, and is used as the address in memory where the data sample is stored. The counter on every board in the system must be enabled to begin counting on the same clock edge so that all data fragments are properly aligned.
A centrally located master clock module generates a low frequency
(25-50 MHz ) clock signal. The asynchronous reset signal is synchronized
to the master clock in this module. Both the low-frequency clock and
the synchronous reset are fanned out and are sent to each crate in the
system. Each crate contains a local clock distribution board. A
programmable delay element is inserted at the clock and reset inputs of
the crate distribution card. This allows for a fine adjustment of timing
at the crate level. The local 250 MHz clock signal is generated from the
low-frequency input clock using a Phase-Locked Loop (PLL) circuit. The
PLL guarantees phase alignment of the 250 MHz clock with the input clock.
The 250 MHz local clock and the reset are fanned out and are sent to each
module in the crate.
Fan out of the clock and reset signals on the master clock module, the crate distribution board, and the front-end boards is done using low-skew (50-100 ps) fan out buffers and employing careful layout techniques (e.g. equal length traces). Distribution of the signals to modules within a crate may be done using short (<1 ft), matched, high-quality coaxial cables.
Since the master clock module and front-end crates may be hundreds of feet apart, we are investigating the use of fiber-optic links in this level of distribution. Care must be taken not to introduce significant jitter into the signals here, as the PLL circuit may have problems locking onto the signal.
A scheme for distributing the low-frequency clock and reset signals to
the crates uses G-link components. G-link is a virtual ribbon cable
interface for the transmission of data. Parallel data (a frame) loaded
into the transmit chip (Tx) is delivered to the receiver chip (Rx) over
a serial channel (fiber) and is reconstructed into its original parallel
form. The serial link is synchronous. Frames may be clocked into the Tx
chip at a rate of 7.5 MHz to 75 MHz . The frame clock is recovered from
the serial data stream by the Rx chip. Individual G-links connect the
master clock module to each crate distribution board. The master clock
serves as the frame clock for each Tx chip, and the Rx chip in each crate
recovers this clock. Reset is specified as a bit asserted in the parallel
data word transmitted, and is synchronized to the clock at each Rx. Many
other ``timing events'' could also be broadcast as unique data patterns to
the crates.