Mott Electronics Logic Setup


 
Step 1.

E (up) and DE (down) signal triggered from the 
E signal with a trigger threshold of -25 mV.

Step 2

E (up) and DE (down) signal triggered from the 
E signal with a trigger threshold of -170 mV.

Step 3

E trigger gate (30ns) and DE trigger gate (5ns). 
Triggered from E signal.

 

Step 4

E signal and ADC gate triggered on E (~55mV), 
ADC gate 85 ns. 
Time difference between E and gate ~20ns.
 

Step 5.

DE signal and ADC gate trigger E signal (~50mv),
Very rare coincidences. 
Often no pulse in DE and thus no ADC gate.

 

Step 6.

DE signal and ADC gate trigger E signal (-125mV) level.
Every High energy E signal has a DE signal. 
Some ADC gates are blocked by the DE veto.

 

Step 7.

Coincidence of E, DE and 125Mhz signals. 
Trigger is the E signal at -45mV.

Step 8.

Coincidence of E, DE, and 125 Mhz. 
Trigger is E at -215mV.
Not always coincident, but clear time structure.

Step 9.

Like Step 8, but time scale is 2 ns. 
Time jitter less than 1 ns.


 

 Site maintenance performed on June 20, 2003
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