The Model V1190B is a 1-unit wide VME 6U module that houses 64 independent Multi-Hit/Multi-Event Time to Digital Conversion channels.
The unit houses 4 hogh Performance TDC chips, developed by CERN/ECP-MIC Division. Resolution canbe set at 100 ps (19 bit dynamics, 52 us FSR), 200ps(19 bit dynamics, 104 us FSR) or 800ps(17 bit dynamics, 104 us FSR). The board houses a 32 kworkds deep Output Buffer, that can be readout via VME(as single data, Block Transfer and Chained Block Transfer) in a completely independent eay from the acquisition itself.
Note: trigger resolution for this unit is 25ns. If  acquisition mode 'trigger matching' is used then you need to have delayed trigger signal also presented on one of  data input of TDC.

For our goals we have used next settings for TDC operation:

• resolution is 100 ps
• detected edge is leading
• number of hits is 16
• acquisition mode: trigger matching
• enable trigger time substruction
• no DMA mode, only FIFO readout
• in CODA *.crl file only low 16 bits of data are used
• base address is 0x10200000 (on board rotary switch: 0x08200000)
  

Configuring of TDC for operation.

To configuring logic of TDC operaions  routines from 'tdc890.o' library(located in "adaqel2: /home/moller/dev/v1190/") are used.
This can be done in  the coda *.crl file(test_TDC.crl - located in "adaqel2:/home/moller/coda/crl/") or using VxWorks terminal.
The file 'tdc890.o' should be downloaded to VME crate using command from VxWorks terminal:
ld < path_to_file/tdc890.o
The detailed description of the functions one can be find in source file 'tdc890.c' located in "adaqel2: /home/moller/dev/v1190/".

Compiation of *.crl file for using with CODA.

To compile '*.crl' code one can type (under moller account on adaqel2) :
tcsh
cd coda2/crl
makelist test_TDC.crl ppc
 

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