G0 Analysis Software Distributions

G0 Analysis Documentation

• A short text guide to using the silo and the batch farm for analysis, last updated Jan 2002. This does need to be updated; but it may still be usful as a guide.
• A guide to using the CVS repository of the G0 analysis software, last updated 8 January 2002.
• Jason's web pages contining links to the Analysis manual.
• Some other packages used in the G0 analysis project are CVS, ROOT and MySQL.
  • The Concurrent Versions System (CVS) website.
  • The MySQL database website.
  • The ROOT Object-Oriented Data Analysis Framework website.

DAQ Documentation

• Signal and high voltage cabling layout.

  • This is a postscript file containing the mapping of all detectors and other signal channels to high voltage channels and signal cables.
    Last updated on 22 Aug 2002.
  • This describes the full connections from the North American detectors to the electronics, for both the Fastbus and the time encoding electronics.
    Last updated on 22 Aug 2002.
  
  

• Rack layout.

  • This is a encapsulated postscript file containing the rack layout.
    Last updated on 19 June 2002.
  
  

• G0 DAQ trigger diagrams, as updated for the chain-test (late spring 2001).

  • Trigger diagram focusing on the GMS and Fastbus control signals; 2001 March 21.
  • Trigger diagram focusing on the main trigger control signals; 2001 March 21.
  • Trigger diagram focusing on the control signals used for the chain-test; 2001 March 21.
  • Trigger diagram showing the "self-trigger" and paddle detector triggers for Octant 7 (NA octant) and Octant 2 (French octant) during the chain-test; 2001 May 15.
  
  

• DAQ information from the 16-17 February 2001 collaboration meeting.

  • Proposed DAQ Configuration Information (15 Feb 2001).
    This note documents my plans for the G0 DAQ system, and describes the order in which I expect the DAQ to develop over the course of the chain test.
    • Postscript of note text, without diagrams
    • Schematic of the main trigger
    • Schematic of the chain-test trigger
    • The hand-drawn schematic of the GMS/Fastbus trigger is not yet available in electronic format. Please send me email to request a copy.
  
  

• Other DAQ related items.

  • Schematics of the G0 Trigger Logic
    • Fastbus trigger schematic, 15 January 2001 -- This shows the trigger and gating signals for the GMS and the fastbus system.
    • Main trigger schematic, 30 January 2001 -- This schematic shows the construction of the main physics trigger signals from the "MPS" and "T120" signals provided by the injector, and the "MRUN" and "E120" control signals produced by the DAQ. The "MRUN" is true when the DAQ is in a run. The "E120" is true when the DAQ is in the 120 Hz running configuration.

      The signals "Beam Disable Counting" and "Beam Next Pulse" will further need to be fanned out to the scalers used to collect the BPM and BCM information. The signals "NA Latch" and "NA Clear" will need to fanned out to the NA scalers.

      The distribution of the "YO" and "LTPO" signals are not shown in this schematic.

    
    

Other tests.

• Fastbus tests; 6 Feb 2001 and 8 Feb 2001.
  To date, the tests with the Fastbus system, in the expected G0 configuration, have exhibited an unacceptable amount of noise.

  The following plots are using a test pulser to produce a signal input to ADC channel 0, while also using the pulser to produce the ADC gate. The signal is input to either the NA splitter or the Orsay splitter, from which it is sent to the ADC. The three splitter channels adjacent to the pulser signal have terminators on a 50 ns cable as their inputs.

  At this point, the 1881M in 50 ohm fixed ground mode seems to reduce the noise to an acceptable level (at least for the NA splitter). We will next try to operate the 1885F in the same mode, and determine if that configuration also has acceptable noise levels. If this is the only mode which has acceptable noise levels, it will necessitate a reconfiguration of the splitters to match the 50 ohm impedance of the ADCs.

  • NA Splitter; 1885F ADC in 100 ohm differential mode -- The horizontal scale is 300 channels wide, corresponding to a range in the incident charge of 15 fC.
  • NA Splitter; 1881M ADC in 50 ohm fixed ground mode -- The horizontal scale is 100 channels wide, corresponding to a range in the incident charge of 5 fC.
  • NA Splitter; 1881M ADC in 102 ohm quasi-differential mode -- The horizontal scale is 100 channels wide, corresponding to a range in the incident charge of 5 fC.
  • Orsay Splitter; 1881M ADC in two modes -- The upper ADC plot is for a test pulser signal being sent through the Orsay splitter, then into the 1881M in 102 ohm quasi-differential mode. The lower ADC plot is for a test pulser signal being sent through the Orsay splitter, then into the 1881M in 50 ohm fixed ground mode.
  • Orsay Splitter; 1881M ADC in 102 ohm quasi-differential mode -- The lower ADC plot is for a test pulser signal being sent through the Orsay splitter; the upper plot has the ground shield of the adjacent splitter channel's cable pressed against the Orsay splitter box.

  Some additional tests were done using an 1885 which could be operated in 50 or 100 ohm input impedance and fixed or floating ground. (Done on 8 Feb 2001)

  • The signal is a pulser signal sent into the NA Splitter; an 1885 is used in four modes--- In all four of these plots, the horizontal scale is 250 channels wide. The pulser signal was fanned out, with one copy sent into the NA splitter and one copy used to generate the ADC gate. The cable for the CFD was plugged into the CFD and the CFD crate power was turned on. Run 5491 (top left) uses the 100 ohm, fixed ground input configuration. Run 5490 (top right) uses 50 ohm, fixed ground inputs. Run 5492 (bottom left) uses 100 ohm, floating ground inputs. Run 5493 (bottom right) uses 50 ohm, floating ground inputs.
    The floating ground (also referred to as quasi-differential by LeCroy) shows less noise than the fixed ground, and the 50 ohm input impedance is better than the 100 ohm.
  • These plots are for one of the adjacent channels from the four runs in the preceding plot--- The horizontal scale is 200 channels wide. These four plots show the ADC channel 3 pedestal for the four ADC input impedance configurations.
  
  
• Fastbus tests; 20 February 2001 - 21 February 2001.
  On 15 Feb 2001, the Fastbus crate used in the above tests was replaced by a different one. The problems with the long outlier data in the pedestal and signal measurements were resolved by this change.
  • 1885F in 100 ohm fixed ground mode, using NA splitter --- The PMT HV are on (FR=1700, FL=1600, BR=1900, BL=1980) but there is no beam in the hall. A 4 MHz clock is used to provide a random trigger. Notice that the pedestals are now much cleaner than when using the other Fastbus crate.
  • 1885F in 100 ohm fixed ground mode, using Orsay splitter --- The pedestals are broader than with the NA splitter; this data was taken using the four channels of the Orsay splitter closest to the splitter's power supply. Also, the Orsay splitter is located next to the HV racks. The PMTs and trigger source are as for the NA splitter test.
  • 1885F in 100 ohm quasi-differential mode, using Orsay splitter --- The splitter channels have been moved, so that the four furthest from the internal supply are used. The ADC has been changed to quasi-differential mode. The PMTs and trigger source are as for the NA splitter test.
  • 1885F in 100 ohm quasi-differential mode, using Orsay splitter --- A total of 100 ns of delay line is used to delay the PMT signals before they enter the Orsay splitter, so that the signals would arrive in the ADC gate. The PMTs and trigger source are as for the NA splitter test.
  A further test used a pulser signal input to either of the two splitters as the signal. The trigger was formed from either this pulser, or another random source (one of the PMTs) to provide both signal and pedestal in this measurement.
  • Comparison of the NA splitter and Orsay splitter using the test pulser signal input. --- The only difference in these configurations was the length of delay before and after each splitter. The NA Splitter had about 50ns of delay on both the input and output; the Orsay splitter had about 100ns of delay on the input and only about 8ns of cable between it and the ADC.