1.) Simulation: An ANSYS simulation is being used to generate the electric field map within a GEM equiped ionization chamber. The GEM geometry has been reduced to a fundamental level using only 1/4 of two staggered holes. The electric field produced by that geometry can by generated using symmetry arguments over the entire GEM foils. Grapical view of GEM Electric Field map.
2.) GEM Power supply: Current Monitor circuit still in design stage. Need to confirm that power supply trip works as advertised. Current Amplifier circuit has been designed and tested. Circuit provides mA output down to 7nA. Design is being transvered from test board to PC board.
3.) Readout: PC board made to house chip connectors which
supply power to the Helix chip and provide access to control lines
(trigger, clock, readout...).
PC board being designed to connect to GEM detector readout
pads. The Helix chip input pads will be wire bonded to
this PC board.
Need LVDS control signals for Helix ship. Clock and trigger
inputs need to conform to the LVDS specs (200 mV sine
waves). Chips have arrived to convert TTL pulses to LVDS
signals and a NIM bin box is being designed.
4.) Detector Design:
5.) Test Apparatus
