Present: Fernando Barbosa, Jian-Ping Chen, Ed Jastrzembski, Krishna Kumar, Bodo Reitz, Xiaochao Zheng

Presentation by Xiaochao: click here
Comments:
(EJ): VME readout could be much faster than 1 word/10ms, could be 0.3ms, thus increase the event rate limit to 3KHz;
(JPC): Should compare ADC spectra with Hypernuclear data;
(KK): Should not use shower/preshower blocks behind the HAPPEX detector (15 rad. length);
(BR): For triggering during HAPPEX, can use S0 .and. S2;
(FB): FADC module with FPGA is not commercially available; (thus the goal of the next test should be mainly on PID performance);
(FB): Please let us (DAQ group) know users' requirement on the FADC asap. The DAQ group is tied with lot of other works (Hall A B C D) but development on the FADC will have a higher priority.  With enought committment It will take 1 year to get the first prototype done and a few more months for more prototypes. The most time consuming part will be the testing.