Jlab R&D Status Report
Negotiations for the transfer of the MEGA/LASS solenoidal magnet to Jlab for use
in the Hall D project began immediately after Larry Cardman sent a letter to
John McClelland officially requesting the magnet. Paul Brindza drafted a
Memorandum of Understanding (MOU) between Los Alamos National Lab and Jefferson Lab.
Doug Tilles has been identified as the Jlab on-site coordinator for dissassembly
and preparation for magnet move.
Paul Brindza, Doug Tilles and Eric Scott (IU) visited Los Alamos in April to
receive training, resolve remaining issues for the MOU, and prepare a
preliminary work plan. A detailed list of activities to prepare for
the magnet move was compiled and issues that needed further
coordination were identified. Since then the draft MOU has been updated to
reflect all stated concerns
and received several rounds of updates from all parties. Paul prepared an
Hazard Control Plan (HCP) for the
work, which received a positive review from the Los Alamos safety officer.
Los Alamos has completed some preliminary tasks in anticipation of the arrival of
the Jlab work crew, including disconnecting the magnet power and removal of the
Helium refrigerator. The work plan calls for two trips by Jlab teams to complete
the preparations for the magnet move.
Doug and Paul are traveling to Los Alamos Sep 9-12 to finalize any MOU details and
schedule the first trip by Jlab technicians to clear the magnet area. We expect that
the MOU can be signed shortly so that work teams can be scheduled for dissassembly.
There have been discussions with IUCF to refurbish the magnet for use in Hall D. A decision
and agreement to have IUCF perform this work clearly needs to made before arrangements can be
made to move the magnet.
All the latest revisions to the civil drawings have been updated and
are consistent with the Design Report. Copies of the drawings can be found in the
High Resolution Pipeline TDC development
A prototype pipeline TDC board based on the COMPAS F1 chip is under design.
Schematics are well advanced.
This prototype, version 1, should be available for testing by the end of the year.
Prototype 1 will be a working module which can be used in
existing experiments, and provide experience with the F1 chip based on a design
which can be adapted to future demands of Hall D.
The plans for the prototype were summarized in June in a series of
view graphs. Here is an outline of the project to date:
Draft JLAB F1 TDC Specification -- Ed Jastrzembski
- July - Aug [Barbosa, Jastrzembski]
Significant design progress for prototype, version 1:
- Prototype board definition and front end test considerations.
- 'Front End' receiver design/termination consideration and connector
scheme to handle low/high resolution configuration.
- FIFO and VME readout/control capability added to prototype 1 design
- Significant work on schematic/ECAD and programmable logic design
- Power supply section defined to allow prototype 1 to be used in
'normal' VME powered card enclosure.
- Serial command sequencer for F1 TDC chips discussed and design near
complete. [ J. Proffitt ]
- Sept - Oct Plans [Barbosa, Jastrzembski, Proffitt]
- Schematic [ designs ] consolidation and verification.
- ECAD file(s) and components will need to be created
- Decision [ discussion ] regarding trigger/clock/Start signal
distribution and other considerations to make the prototype
backward compatible with existing VME systems. This may impact the 'final'
design scheme. Prototype 1 will allow for these signals
to be input from front panel.
- Circuit board design. [ Component placement and routing ] This will
be a critical step and demand an expert!
- Circuit board design verification using ECAD etc.
- DEFINE TESTING REQUIREMENTS
- Order boards and components.
- Nov - Dec Projection
- Verify components for assembly
- Surface mount assembly process
- Front panel design and fabrication
- Firmware for FPGA and any other logic will need to be downloaded and
Computers have been ordered for testing grid software in collaboration with FSU
and the JLab Computing dept. They should arrive soon.
Evio ("CODA") format has been tentatively chosen as the binary raw data format,
and possibly for all binary formats if collaborators agree. XML has been chosen
for ASCII files. The CODA evio package has been expanded and improved to meet
Hall D needs. Converters between evio and xml have been written and tested on
Hall C evio data, and are proving useful for Hall C already.
Improvements to the slow controls package CDEV have been explored. A test
publish/subscribe service has been implemented by Elliott Wolin
as a protoytpe for Hall D use.
Results were presented at the CHEP01 conference.