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bor_roc.h
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1 //
2 // Data structures for holding module configuration information
3 // read back from the modules themselves for packaging into the
4 // Beginning Of Run (BOR) record.
5 //
6 // IMPORTANT: THIS FILE IS MAINTAINED IN 2 REPOSITORIES!
7 //
8 // Before making changes to this file, keep these points in mind:
9 //
10 // 1. This file is maintained in separate repositories since the
11 // code that generates the BOR during data taking resides
12 // in the online repository and the code that must interpret
13 // it resides in the offline repository. The locations of the
14 // file in the two repositories are:
15 //
16 // https://halldsvn.jlab.org/repos/trunk/online/daq/vme/src/rcm/monitor/bor_roc.h
17 // https://github.com/JeffersonLab/sim-recon/tree/master/src/libraries/DAQ/bor_roc.h
18 //
19 // Any changes MUST be made in both places!
20 //
21 // 2. The BOR data structures are stored directly in the raw data
22 // files. Any changes made will not be available in existing
23 // data files. Any modifications here should be added to the
24 // end of the data structures so there is some (small) hope
25 // of being able to handle both old and new raw data files.
26 //
27 // 3. Any items added should either be uint32_t or an array of
28 // uint16_t with and even number of elements. This is so
29 // the data will stay close packed on 64bit platforms where
30 // the compiler will tend to add padding bytes so that 64bit
31 // types end up on 64bit address boundaries.
32 //
33 //
34 // The CODA driver libraries for these modules define structs
35 // that map the entire register space of the module (e.g.
36 // "fadc_struct" in fadcLib.h). We are only interested in a
37 // subset of those values so we define different structures here.
38 // Where possible, these use the same names for data members
39 // that the CODA drivers used.
40 //
41 // An instance of the ModulesConfigBOR structure is included
42 // in the ROC shared memory section defined in shmem_roc.h .
43 // The values are filled from the ROL (e.g. vme_list.c) using
44 // calls to the bor_utils.cc library in the rol_1 source directory.
45 //
46 // Access to the ModulesConfigBOR record from outside of the ROC
47 // is made via the shared memory server. The hdBOR program is
48 // run at the start of data taking to gather this information,
49 // format it into EVIO and write it to the data stream. Flags
50 // are set to tell the Event Recorder to write it to the
51 // beginning of every file it creates.
52 //
53 // The BOR is uppacked and put into JANA objects in the DAQ
54 // library when the data is read in. They show up in classes
55 // like "Df125BORConfig", and "DF1TDCBORConfig" that inherit
56 // from these structures.
57 //
58 // Any questions regarding this system can be referred to:
59 //
60 // davidl@jlab.org
61 //
62 
63 #ifndef _BOR_ROC_H_
64 #define _BOR_ROC_H_
65 
66 #include <stdint.h>
67 
68 typedef struct{
69 
70  uint32_t rocid;
71  uint32_t slot;
72 
73  // This based on information in "Programming_the_FADCV2_11_25_13.pdf"
74 
75  uint32_t version; // 0x0000
76  uint32_t ctrl1; // 0x0008
77  uint32_t ctrl2; // 0x000C
78  uint32_t blk_level; // 0x0010
79  uint32_t delay; // 0x0024
80  uint32_t itrig_cfg; // 0x0028
81  uint16_t dac[16]; // 0x0050 - 0x006C
82  uint32_t trig21_delay; // 0x0088
83  uint32_t serial_number[3]; // 0x00E4 - 0x00EC
84 
85  uint32_t adc_status[3]; // 0x0100 - 0x0108
86  uint32_t adc_config[4]; // 0x010C - 0x0118
87  uint32_t adc_ptw; // 0x011C
88  uint32_t adc_pl; // 0x0120
89  uint32_t adc_nsb; // 0x0124
90  uint32_t adc_nsa; // 0x0128
91  uint16_t adc_thres[16]; // 0x012C - 0x0148
92  uint32_t adc_pedestal[16]; // 0x0158 - 0x0194
93  uint32_t config6; // 0x014C
94  uint32_t config7; // 0x0150
95  uint32_t config3; // 0x0198
96 }f250config;
97 
98 typedef struct {
99 
100  uint32_t version; // 0xN000
101  uint32_t nw; // 0xN058
102  uint32_t pl; // 0xN05C
103  uint32_t threshold[6]; // 0xN070
104  uint32_t config1; // 0xN088
105  uint32_t config2; // 0xN090
106  uint32_t ped_sf; // 0xN0A0
107  uint32_t timing_thres_lo[3]; // 0xN0A0 - 0xN0AC
108  uint32_t ie; // 0xN0B0
109  uint32_t timing_thres_hi[2]; // 0xN0B4 - 0xN0B8
111 
112 typedef struct {
113 
114  uint32_t rocid;
115  uint32_t slot;
116 
117  // This based on information in "fadc125_register_map_9.pdf"
118  // and info found in fa125Lib.h
119 
120  uint32_t board_id; // 0x0000
121  uint32_t version; // 0x0008
122  uint32_t clock; // 0x000C
123  uint32_t serial[4]; // 0x0020 - 0x002C
124  uint32_t temperature[2]; // 0x0030 - 0x0034
125  uint32_t ctrl1; // 0x0044
126 
128 
129  uint32_t proc_version; // 0xD000
130  uint32_t proc_csr; // 0xD004
131  uint32_t proc_trigsrc; // 0xD008
132  uint32_t proc_ctrl2; // 0xD00C
133  uint32_t proc_blocklevel; // 0xD014
134 }f125config;
135 
136 typedef struct {
137 
138  uint32_t rocid;
139  uint32_t slot;
140 
141  uint32_t version; // 0x0000
142  uint32_t ctrl; // 0x0008
143  uint32_t blocklevel; // 0x0010
144 
145  uint32_t nchips;
146  uint32_t f1registers[8][16];
147 }F1TDCconfig;
148 
149 
150 typedef struct {
151 
152  uint32_t rocid;
153  uint32_t slot;
154 
155  uint32_t edge_resolution;
158  uint16_t almostFullLevel; // 0x1022
159  uint16_t bltEventNumber; // 0x1024
160  uint16_t firmwareRev; // 0x1026
161 
162 
164 
165 // Container struct that can hold all module
166 // configurations for this crate in a statically
167 // sized memory space appropriate for using with
168 // a shared memory section.
169 typedef struct {
170  uint32_t Nf250;
171  uint32_t Nf125;
172  uint32_t NF1TDC;
173  uint32_t Ncaen1190;
174 
175  f250config f250[21];
176  f125config f125[21];
177  F1TDCconfig F1TDC[21];
178  caen1190config caen1190[21];
180 
181 #endif //_BOR_ROC_H_
uint32_t version
Definition: bor_roc.h:75
uint32_t Nf250
Definition: bor_roc.h:170
uint32_t version
Definition: bor_roc.h:121
uint32_t version
Definition: bor_roc.h:141
uint32_t proc_blocklevel
Definition: bor_roc.h:133
uint32_t config6
Definition: bor_roc.h:93
uint32_t Ncaen1190
Definition: bor_roc.h:173
uint32_t config7
Definition: bor_roc.h:94
uint32_t proc_csr
Definition: bor_roc.h:130
uint32_t blk_level
Definition: bor_roc.h:78
uint32_t adc_ptw
Definition: bor_roc.h:87
uint16_t firmwareRev
Definition: bor_roc.h:160
uint32_t NF1TDC
Definition: bor_roc.h:172
uint32_t ctrl1
Definition: bor_roc.h:76
uint32_t board_id
Definition: bor_roc.h:120
uint32_t trig21_delay
Definition: bor_roc.h:82
uint32_t edge_resolution
Definition: bor_roc.h:155
uint32_t slot
Definition: bor_roc.h:71
uint32_t rocid
Definition: bor_roc.h:138
uint32_t config2
Definition: bor_roc.h:105
uint32_t adc_pl
Definition: bor_roc.h:88
uint32_t blocklevel
Definition: bor_roc.h:143
uint32_t ie
Definition: bor_roc.h:108
uint32_t clock
Definition: bor_roc.h:122
uint32_t ped_sf
Definition: bor_roc.h:106
uint32_t adc_nsa
Definition: bor_roc.h:90
uint32_t pl
Definition: bor_roc.h:102
uint32_t slot
Definition: bor_roc.h:153
uint32_t delay
Definition: bor_roc.h:79
uint32_t ctrl1
Definition: bor_roc.h:125
uint32_t version
Definition: bor_roc.h:100
uint32_t slot
Definition: bor_roc.h:139
uint16_t bltEventNumber
Definition: bor_roc.h:159
uint32_t proc_ctrl2
Definition: bor_roc.h:132
uint32_t adc_nsb
Definition: bor_roc.h:89
uint32_t config3
Definition: bor_roc.h:95
uint32_t double_hit_resolution
Definition: bor_roc.h:156
uint32_t itrig_cfg
Definition: bor_roc.h:80
uint32_t nw
Definition: bor_roc.h:101
uint32_t config1
Definition: bor_roc.h:104
uint32_t nchips
Definition: bor_roc.h:145
uint32_t proc_version
Definition: bor_roc.h:129
uint32_t rocid
Definition: bor_roc.h:70
uint32_t rocid
Definition: bor_roc.h:114
uint32_t slot
Definition: bor_roc.h:115
uint32_t proc_trigsrc
Definition: bor_roc.h:131
uint16_t almostFullLevel
Definition: bor_roc.h:158
uint32_t Nf125
Definition: bor_roc.h:171
uint32_t max_hits_per_event
Definition: bor_roc.h:157
uint32_t ctrl2
Definition: bor_roc.h:77
uint32_t rocid
Definition: bor_roc.h:152
uint32_t ctrl
Definition: bor_roc.h:142