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mc2coda_modules.h
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1 /* mc2coda Library
2  Includes module data generating functions */
3 
4  #include <DAQ/daq_param_type.h>
5 
6 void GetPedestals(uint32_t *peds, uint32_t Npeds);
7 
8 #define SUPPRESS_DRIFT_CHAMBER_HITS_OVERFLOW_WARNINGS 1
9 
10 
11 /* FADC 250 Paramters */
12 #define FADC250_MAX_CHAN 16
13 #define FADC250_MAX_HITS 4
14 #define FADC250_MAX_WINDOW 512
15 #define FADC250_MAX_LATENCY 2048
16 #define FADC250_MAX_NSB 512
17 #define FADC250_MAX_NSA 512
18 #define FADC250_WINDOW_WIDTH 50
19 
20 /* FADC 250 Macros */
21 #define FADC250_BL_HEADER(slot,blnum,cnt) {*dabufp++ = 0x80000000 | (slot << 22) | (FADC250 << 18) | ((blnum&0x3ff) << 8) | cnt; }
22 #define FADC250_BL_TRAILER(slot,nwords) {*dabufp++ = 0x88000000 | (slot << 22) | nwords; }
23 
24 #define FADC250_EV_HEADER(slot,trig) {*dabufp++ = 0x90000000 | (slot << 22) | (trig&0x3fffff); }
25 #define FADC250_EV_TS_LOW(timestamp) {*dabufp++ = 0x98000000 | (timestamp&(0x0000000000ffffffLLU)); }
26 #define FADC250_EV_TS_HIGH(timestamp) {*dabufp++ = (timestamp&(0x0000ffffff000000LLU)) >> 24; }
27 #define FADC250_EV_PARAM1(nsb,nsa,pl) {*dabufp++ = (nsb) << 20 | (nsa) << 11 | pl; }
28 
29 #define FADC250_RW_HEADER(chan,ww) {*dabufp++ = 0xA0000000 | (chan << 23) | ww ; }
30 #define FADC250_RW_DATA(s1,s2) {*dabufp++ = (s1 << 16) | s2 ; }
31 
32 #define FADC250_WI_SUM(chan,sum) {*dabufp++ = 0xA8000000 | (chan << 23) | (sum&0x3fffff) ; }
33 
34 #define FADC250_RP_HEADER(chan,pn,fs) {*dabufp++ = 0xB0000000 | (chan << 23) | (pn << 21) | (fs) ; }
35 #define FADC250_RP_DATA(s1,s2) {*dabufp++ = (s1 << 16) | s2 ; }
36 
37 #define FADC250_PI_SUM(chan,pn,sum) {*dabufp++ = 0xB8000000 | (chan << 23) | (pn << 21) | (sum&0x7ffff) ; }
38 #define FADC250_PI_TIME(chan,pn,time) {*dabufp++ = 0xC0000000 | (chan << 23) | (pn << 21) | (time&0x7ffff); }
39 #define FADC250_PI_PED(chan,pn,ped,peak) {*dabufp++ = 0xD0000000 | (chan << 23) | (pn << 21) | ((ped&0x1ff)<<12) | (peak&0xfff); }
40 
41 #define FADC250_FILLER {*dabufp++ = 0xF8000000; }
42 
43 
44 int
45 fadc250_write_data (CODA_EVENT_INFO *event, int roc, int slot, int mode)
46 {
47 
48  int ii, jj, chan, hcnt, nwords;
49  uint32_t eventNum;
50  uint64_t timestamp;
51  unsigned int *start = dabufp;
52  CODA_HIT_INFO *hit;
53  CODA_HIT_INFO *chit[MAX_HITS_PER_CHAN];
54 
55  eventNum = (event->eventid)&0xffffffff;
56  timestamp = (event->trigtime);
57  hcnt = event->hcount[(roc-1)][(slot-1)];
58 
59  FADC250_BL_HEADER(slot,eventNum,1);
60  FADC250_EV_HEADER(slot,eventNum);
61  FADC250_EV_TS_LOW(timestamp);
62 
63  /*printf("fadc250:_write_data: DEBUG: %d hits available"
64  * " for slot %d roc %d.\n",hcnt, slot, roc);
65  */
66 
67  // Get pedestal values (possibly randmized)
68  uint32_t peds[FADC250_MAX_CHAN+1];
69  GetPedestals(peds, FADC250_MAX_CHAN+1);
70 
71  /*Loop over all channels */
72  for (chan=0; chan<FADC250_MAX_CHAN; chan++) {
73 
74  /* check for all hits for this channel */
75  jj=0;
76  for (ii=0; ii<hcnt; ii++) {
77  hit = (CODA_HIT_INFO *) &event->hits[(roc-1)][(slot-1)][ii];
78  /* printf("%d %d %d %d\n",hit->crate_id,hit->slot_id,
79  * hit->chan_id,hit->module_id);
80  */
81  if ( (roc == hit->crate_id) && (slot == hit->slot_id) &&
82  (chan == hit->chan_id) && (hit->module_id == FADC250) &&
83  (hit->module_mode == mode) )
84  {
85  /* printf("fadc250:_write_data: DEBUG: found hit %d for roc"
86  * " %d slot %d chan %d.\n",jj, roc,slot,chan);
87  */
88 
89  chit[jj] = hit;
90  jj++;
91  if (jj >= MAX_HITS_PER_CHAN) {
92  printf("fadc250_write_data: ERROR: HIT overflow (%d) for "
93  "crate,slot,chan = %d,%d,%d (Bank will be corrupt)\n",
94  jj,roc,slot,chan);
95  return 0;
96  }
97  else if (jj > FADC250_MAX_HITS) {
98  printf("fadc250_write_data: WARN: Too many hits (%d) for"
99  " (crate, slot, chan) = %d, %d, %d (truncating)\n",
100  jj,roc,slot,chan);
101  jj = FADC250_MAX_HITS;
102  }
103  }
104  }
105  /* printf("write hit data %d\n",jj); */
106  uint32_t ped = peds[FADC250_MAX_CHAN]; // common pedestal for all channels
107  for (ii=0; ii < jj; ii++) {
108  uint32_t peak = ped + chit[ii]->hdata[0]/10; // Assume pulse is 20samples(=80ns) so area is ~0.5*b*h=pi -> h=pi/(b/2) where b=20samples
109  uint32_t sum = chit[ii]->hdata[0] + ped*FADC250_WINDOW_WIDTH;
110  FADC250_PI_SUM(chan,ii,sum);
111  FADC250_PI_TIME(chan,ii,chit[ii]->hdata[1]);
112  FADC250_PI_PED(chan,ii,(ped + peds[chan]),peak); // measured pedestal has additional stochastic element
113  }
114  }
115 
116  nwords = dabufp - start;
117  if ((nwords%2) == 0) {
118  FADC250_FILLER;
119  nwords += 2;
120  FADC250_BL_TRAILER(slot,nwords);
121  } else {
122  nwords += 1;
123  FADC250_BL_TRAILER(slot,nwords);
124  }
125 
126  if (nwords%4 != 0) {
127  FADC250_FILLER;
128  FADC250_FILLER;
129  nwords += 2;
130  }
131 
132  return nwords;
133 }
134 
135 
136 /* FADC 125 Paramters */
137 #define FADC125_MAX_CHAN 72
138 #define FADC125_MAX_HITS 4
139 #define FADC125_MAX_WINDOW 512
140 #define FADC125_MAX_LATENCY 2048
141 #define FADC125_MAX_NSB 512
142 #define FADC125_MAX_NSA 512
143 #define FADC125_WINDOW_WIDTH 50
144 
145 /* FADC 125 Macros */
146 #define FADC125_BL_HEADER(slot,blnum,cnt) {*dabufp++ = 0x80000000 | (slot << 22) | (FADC125 << 18) | ((blnum&0x3ff) << 8) | cnt; }
147 #define FADC125_BL_TRAILER(slot,nwords) {*dabufp++ = 0x88000000 | (slot << 22) | nwords; }
148 
149 #define FADC125_EV_HEADER(slot,trig) {*dabufp++ = 0x90000000 | (slot << 22) | (trig&0x3fffff); }
150 #define FADC125_EV_TS_LOW(timestamp) {*dabufp++ = 0x98000000 | (timestamp&(0x0000000000ffffffLLU)); }
151 #define FADC125_EV_TS_HIGH(timestamp) {*dabufp++ = (timestamp&(0x0000ffffff000000LLU)) >> 24; }
152 
153 #define FADC125_RW_HEADER(chan,ww) {*dabufp++ = 0xA0000000 | (chan << 20) | (ww&0x1fffff) ; }
154 #define FADC125_RW_DATA(s1,s2) {*dabufp++ = (s1 << 16) | s2 ; }
155 
156 #define FADC125_WI_SUM(chan,sum) {*dabufp++ = 0xA8000000 | (chan << 20) | (sum&0x1fffff) ; }
157 
158 #define FADC125_RP_HEADER(chan,pn,fs) {*dabufp++ = 0xB0000000 | (chan << 20) | (pn << 18) | (fs&0x3ffff) ; }
159 #define FADC125_RP_DATA(s1,s2) {*dabufp++ = (s1 << 16) | s2 ; }
160 
161 #define FADC125_PI_SUM(chan,sum) {*dabufp++ = 0xB8000000 | (chan << 20) | (sum&0xfffff) ; }
162 #define FADC125_PI_TIME(chan,qf,time) {*dabufp++ = 0xC0000000 | (chan << 20) | (qf << 18) | (time&0xffff); }
163 #define FADC125_PI_PED(chan,pn,ped,peak) {*dabufp++ = 0xD0000000 | ((chan << 23)&0x0f) | (pn << 21) | ((ped&0x1ff)<<12) | (peak&0xfff) ; }
164 
165 #define FADC125_FILLER {*dabufp++ = 0xF8000000; }
166 
167 
168 int
169 fadc125_write_data (CODA_EVENT_INFO *event, int roc, int slot, int mode)
170 {
171 
172  int ii, jj, chan, hcnt, nwords;
173  uint32_t eventNum;
174  uint64_t timestamp;
175  unsigned int *start = dabufp;
176  CODA_HIT_INFO *hit;
177  CODA_HIT_INFO *chit[MAX_HITS_PER_CHAN];
178 
179  eventNum = (event->eventid)&0xffffffff;
180  timestamp = (event->trigtime);
181  hcnt = event->hcount[(roc-1)][(slot-1)];
182 
183  /* Global timestamp is in 4ns ticks. The local clock on the FADC 125
184  * is half that so change timestamp to 8ns ticks (divide by two).
185  */
186  timestamp = timestamp >> 1;
187 
188  // Get pedestal values (possibly randmized)
189  uint32_t peds[FADC125_MAX_CHAN+1];
190  GetPedestals(peds, FADC125_MAX_CHAN+1);
191 
192  FADC125_BL_HEADER(slot,eventNum,1);
193  FADC125_EV_HEADER(slot,eventNum);
194  FADC125_EV_TS_LOW(timestamp);
195 
196  /* printf("fadc125_write_data: %d hits checking slot %d roc %d.\n",
197  * hcnt, slot, roc);
198  */
199 
200  /*Loop over all channels */
201  for (chan=0; chan < FADC125_MAX_CHAN; chan++) {
202 
203  /* check for all hits for this channel */
204  jj=0;
205  for (ii=0; ii < hcnt; ii++) {
206  hit = (CODA_HIT_INFO *) &event->hits[(roc-1)][(slot-1)][ii];
207  /* printf("%d %d %d %d\n",hit->crate_id,hit->slot_id,
208  * hit->chan_id,hit->module_id);
209  */
210  if ( (roc == hit->crate_id) && (slot == hit->slot_id) &&
211  (chan == hit->chan_id) && (hit->module_id == FADC125) &&
212  (hit->module_mode == mode) )
213  {
214  /* printf("fadc125:_write_data: DEBUG: found hit for crate"
215  * " %d slot %d chan %d.\n",roc,slot,chan);
216  */
217  chit[jj] = hit;
218  jj++;
219  if (jj >= MAX_HITS_PER_CHAN) {
220  printf("fadc125_write_data: ERROR: HIT overflow (%d)"
221  " for (crate, slot, chan) = %d, %d, %d\n",
222  jj,roc,slot,chan);
223  printf("fadc125_write_data: ERROR: "
224  "ROC Bank will be corrupted\n");
225  return 0;
226  }
227  else if (jj > FADC125_MAX_HITS) {
228 #ifndef SUPPRESS_DRIFT_CHAMBER_HITS_OVERFLOW_WARNINGS
229  printf("fadc125_write_data: WARN: Too many hits (%d)"
230  " for (crate, slot, chan) = %d, %d, %d\n",
231  jj,roc,slot,chan);
232 #endif
233  jj = FADC125_MAX_HITS;
234  }
235  }
236  }
237  /* printf("write hit data %d\n",jj); */
238  uint32_t ped = peds[FADC125_MAX_CHAN]; // common pedestal for all channels
239  for (ii=0; ii < jj; ii++) {
240  uint32_t peak = ped + chit[ii]->hdata[0]/10; // Assume pulse is 20samples(=160ns) so area is ~0.5*b*h=pi -> h=pi/(b/2) where b=20samples
241  uint32_t sum = chit[ii]->hdata[0] + ped*FADC125_WINDOW_WIDTH;
242  FADC125_PI_SUM(chan, sum);
243  FADC125_PI_TIME(chan,0,chit[ii]->hdata[1]); // always make quality factor 0
244  FADC125_PI_PED(chan,ii,(ped + peds[chan]),peak); // measured pedestal has additional stochastic element
245  // f125 generally doesn't support multiple pulses so only record first one
246  break;
247  }
248  }
249 
250  nwords = dabufp - start;
251  if ((nwords%2) == 0) {
252  FADC125_FILLER;
253  nwords += 2;
254  FADC125_BL_TRAILER(slot,nwords);
255  } else {
256  nwords += 1;
257  FADC125_BL_TRAILER(slot,nwords);
258  }
259 
260  if (nwords%4 != 0) {
261  FADC125_FILLER;
262  FADC125_FILLER;
263  nwords += 2;
264  }
265 
266  return nwords;
267 }
268 
269 
270 /* F1TDC 32 Channel Parameters */
271 #define F1TDC32_MAX_CHAN 32
272 #define F1TDC32_MAX_HITS 8
273 #define F1TDC32_MAX_CHIPS 8
274 
275 
276 /* F1TDC 32 channel Macros */
277 #define F1TDC32_BL_HEADER(slot,blnum,cnt) {*dabufp++ = 0x80000000 | (slot << 22) | (F1TDC32 << 18) | ((blnum&0x3ff) << 8) | cnt; }
278 #define F1TDC32_BL_TRAILER(slot,nwords) {*dabufp++ = 0x88000000 | (slot << 22) | nwords; }
279 
280 #define F1TDC32_EV_HEADER(slot,trig) {*dabufp++ = 0x90000000 | (slot << 22)| (trig&0x3fffff); }
281 #define F1TDC32_EV_TS_LOW(timestamp) {*dabufp++ = 0x98000000 | (timestamp&(0x0000000000ffffffLLU)); }
282 #define F1TDC32_EV_TS_HIGH(timestamp) {*dabufp++ = (timestamp&(0x000000ffff000000LLU)) >> 24; }
283 
284 
285 // These changed based on the F1TDC_V2_V3_4_29_14.pdf document
286 //#define F1TDC32_F1_HEADER(cdata,evt,trig,chan) {*dabufp++ = 0xC0000000 | (cdata << 24) | ((evt&0x1ff) << 16) | (chan) ; }
287 //#define F1TDC32_F1_DATA(cdata,chan,time) {*dabufp++ = 0xB8000000 | (cdata << 24) | (chan << 16) | (time&0xffff); }
288 //#define F1TDC32_F1_TRAILER(cdata,evt,trig,chan) {*dabufp++ = 0xA8000000 | (cdata << 24) | ((evt&0x1ff) << 16) | (chan) ; }
289 #define F1TDC32_F1_HEADER(cdata,chip,chan_on_chip,trig,trig_time) {*dabufp++ = 0xC0000000 | ((cdata&0x1F) << 22) | (0 << 23) | (chip << 3) | (chan_on_chip << 0) | ((trig&0x3f) << 16) | ((trig_time&0x1ff) << 7); }
290 #define F1TDC32_F1_DATA(cdata,chip,chan_on_chip,time) {*dabufp++ = 0xB8000000 | ((cdata&0x1F) << 22) | (1 << 23) | (chip << 19) | (chan_on_chip << 16) | (time&0xffff); }
291 
292 #define F1TDC32_FILLER(slot) {*dabufp++ = 0xF8000000 | (slot << 22); }
293 
294 #define F1TDC32_CHIP_NUM(chan) (chan >> 2)
295 #define F1TDC32_CHAN_ON_CHIP(chan) ((chan & 0x03) << 1)
296 
297 int
298 f1tdc32_write_data (CODA_EVENT_INFO *event, int roc, int slot, int mode)
299 {
300 
301  int ii, jj, chan, hcnt, nwords;
302  int chip, chan_on_chip;
303  uint64_t tsdiv;
304  uint32_t ts, cdata;
305  uint32_t eventNum;
306  uint64_t timestamp;
307  unsigned int *start = dabufp;
308  CODA_HIT_INFO *hit;
309  CODA_HIT_INFO *chit[MAX_HITS_PER_CHAN];
310 
311  eventNum = (event->eventid)&0xffffffff;
312  timestamp = (event->trigtime);
313  hcnt = event->hcount[(roc-1)][(slot-1)];
314 
315  /* Set default value for cdata bits - 3 bits - 100b = 0x4
316  * res locked, ouput fifo ok, hit fifo ok
317  */
318  cdata = 0x4;
319 
320  /* Timestamp is in 4 ns ticks. We need to convert to
321  * F1 clocks = 250/8 = 31.25MHz = 32ns/tick
322  */
323  tsdiv = (timestamp >> 3);
324  ts = tsdiv&0xffffffff;
325 
326 
327  F1TDC32_BL_HEADER(slot,eventNum,1);
328  F1TDC32_EV_HEADER(slot,eventNum);
329  F1TDC32_EV_TS_LOW(tsdiv);
330 
331  /* printf("f1tdc32:_write_data: %d hits checking slot"
332  * " %d roc %d.\n",hcnt, slot, roc);
333  */
334 
335  /*Loop over all channels */
336  for (chan=0; chan<F1TDC32_MAX_CHAN; chan++) {
337 
338  chip = F1TDC32_CHIP_NUM(chan);
339  chan_on_chip = F1TDC32_CHAN_ON_CHIP(chan);
340 
341  /* Check for outputing Chip Header */
342  if (chan_on_chip == 0) {
343  //F1TDC32_F1_HEADER(cdata, (eventNum&0x3f),(ts&0x1ff),chan);
344  F1TDC32_F1_HEADER(cdata,chip, 7,(eventNum&0x3f), (ts&0x1ff));
345  }
346 
347  /* check for all hits for this channel */
348  jj=0;
349  for (ii=0; ii<hcnt; ii++) {
350  hit = (CODA_HIT_INFO *) &event->hits[(roc-1)][(slot-1)][ii];
351  /* printf("%d %d %d %d\n",hit->crate_id,hit->slot_id,
352  * hit->chan_id,hit->module_id);
353  */
354  if ( (roc == hit->crate_id) && (slot == hit->slot_id) &&
355  (chan == hit->chan_id)&& (hit->module_id == F1TDC32) &&
356  (hit->module_mode == mode) )
357  {
358  /* printf("f1tdc32:_write_data: DEBUG: found hit for crate %d"
359  * " slot %d chan %d.\n",roc,slot,chan);
360  */
361 
362  chit[jj] = hit;
363  jj++;
364  if (jj >= F1TDC32_MAX_HITS) {
365  printf("f1tdc32_write_data: ERROR: Too many hits for channel\n");
366  jj--;
367  break;
368  }
369  }
370  }
371  /* printf("write hit data %d\n",jj); */
372  for (ii=0; ii < jj; ii++) {
373  /* printf("f1tdc32:_write_data: DEBUG: found hit for crate %d"
374  * " slot %d chan %d (chip %d chan on chip %d).\n",
375  * roc,slot,chan,chip,chan_on_chip);
376  */
377  F1TDC32_F1_DATA(cdata,chip,chan_on_chip,chit[ii]->hdata[0]);
378  }
379 
380  /* Check for outputing chip trailer */
381 #if 0
382  if (chan == 31) {
383  F1TDC32_F1_TRAILER(cdata,(eventNum&0x3f),(ts&0x1ff),chan);
384  }
385 #endif
386 
387  }
388 
389  nwords = dabufp - start;
390  if ((nwords%2) == 0) {
391  F1TDC32_FILLER(slot);
392  nwords += 2;
393  F1TDC32_BL_TRAILER(slot,nwords);
394  } else {
395  nwords += 1;
396  F1TDC32_BL_TRAILER(slot,nwords);
397  }
398 
399  if (nwords%4) {
400  F1TDC32_FILLER(slot);
401  F1TDC32_FILLER(slot);
402  nwords += 2;
403  }
404 
405  return nwords;
406 }
407 
408 
409 /* F1TDC 48 Channel Parameters */
410 #define F1TDC48_MAX_CHAN 48
411 #define F1TDC48_MAX_HITS 8
412 #define F1TDC48_MAX_CHIPS 6
413 
414 
415 /* F1TDC 48 channel Macros */
416 #define F1TDC48_BL_HEADER(slot,blnum,cnt) {*dabufp++ = 0x80000000 | (slot << 22) | (F1TDC48 << 18) | ((blnum&0x3ff) << 8) | cnt; }
417 #define F1TDC48_BL_TRAILER(slot,nwords) {*dabufp++ = 0x88000000 | (slot << 22) | nwords; }
418 
419 #define F1TDC48_EV_HEADER(slot,trig) {*dabufp++ = 0x90000000 | (slot << 22) | (trig&0x3fffff); }
420 #define F1TDC48_EV_TS_LOW(timestamp) {*dabufp++ = 0x98000000 | (timestamp&(0x0000000000ffffffLLU)); }
421 #define F1TDC48_EV_TS_HIGH(timestamp) {*dabufp++ = (timestamp&(0x0000ffffff000000LLU)) >> 24; }
422 
423 
424 // These changed based on the F1TDC_V2_V3_4_29_14.pdf document
425 //#define F1TDC48_F1_HEADER(cdata,evt,trig,chan) {*dabufp++ = 0xA0000000 | (cdata << 24) | ((evt&0x1ff) << 16) | (chan); }
426 //#define F1TDC48_F1_DATA(cdata,chan,time) {*dabufp++ = 0xB0800000 | (cdata << 24) | (chan << 16) | (time&0xffff); }
427 //#define F1TDC48_F1_TRAILER(cdata,evt,trig,chan) {*dabufp++ = 0xA8000000 | (cdata << 24) | ((evt&0x1ff) << 16) | (chan); }
428 #define F1TDC48_F1_HEADER(cdata,chip,chan_on_chip,trig,trig_time) {*dabufp++ = 0xC0000000 | ((cdata&0x1F) << 22) | (0 << 23) | (chip << 3) | (chan_on_chip << 0) | ((trig&0x3f) << 16) | ((trig_time&0x1ff) << 7); }
429 #define F1TDC48_F1_DATA(cdata,chip,chan_on_chip,time) {*dabufp++ = 0xB8000000 | ((cdata&0x1F) << 22) | (1 << 23) | (chip << 19) | (chan_on_chip << 16) | (time&0xffff); }
430 
431 #define F1TDC48_FILLER(slot) {*dabufp++ = 0xF8000000 | (slot << 22); }
432 
433 #define F1TDC48_CHIP_NUM(chan) (chan >> 3)
434 #define F1TDC48_CHAN_ON_CHIP(chan) (chan & 0x07)
435 
436 
437 int
438 f1tdc48_write_data (CODA_EVENT_INFO *event, int roc, int slot, int mode)
439 {
440 
441  int ii, jj, chan, hcnt, nwords;
442  int chip, chan_on_chip;
443  uint64_t tsdiv;
444  uint32_t ts, cdata;
445  uint32_t eventNum;
446  uint64_t timestamp;
447  unsigned int *start = dabufp;
448  CODA_HIT_INFO *hit;
449  CODA_HIT_INFO *chit[MAX_HITS_PER_CHAN];
450 
451  eventNum = (event->eventid)&0xffffffff;
452  timestamp = (event->trigtime);
453  hcnt = event->hcount[(roc-1)][(slot-1)];
454 
455  /* Set default value for cdata bits - 3 bits - 100b = 0x4
456  * res locked, ouput fifo ok, hit fifo ok
457  */
458  cdata = 0x4;
459 
460  /* Timestamp is in 4 ns ticks. We need to convert to
461  * F1 clocks = 250/8 = 31.25MHz = 32ns/tick
462  */
463  tsdiv = (timestamp >> 3);
464  ts = tsdiv&0xffffffff;
465 
466 
467  F1TDC48_BL_HEADER(slot,eventNum,1);
468  F1TDC48_EV_HEADER(slot,eventNum);
469  F1TDC48_EV_TS_LOW(tsdiv);
470 
471  /* printf("f1tdc48_write_data: %d hits checking slot %d roc %d.\n",
472  * hcnt, slot, roc);
473  */
474 
475  /* Loop over all channels */
476  for (chan=0; chan < F1TDC48_MAX_CHAN; chan++) {
477 
478  chip = F1TDC48_CHIP_NUM(chan);
479  chan_on_chip = F1TDC48_CHAN_ON_CHIP(chan);
480 
481  /* Check for outputing Chip Header */
482  if (chan_on_chip == 0) {
483  //F1TDC48_F1_HEADER(cdata, (eventNum&0x3f),(ts&0x1ff),0);
484  F1TDC48_F1_HEADER(cdata,chip,7,(eventNum&0x3f), (ts&0x1ff));
485  }
486 
487  /* check for all hits for this channel */
488  jj=0;
489  for (ii=0; ii < hcnt; ii++) {
490  hit = (CODA_HIT_INFO *) &event->hits[(roc-1)][(slot-1)][ii];
491  /* printf("%d %d %d %d\n",hit->crate_id,hit->slot_id,
492  * hit->chan_id,hit->module_id);
493  */
494  if ( (roc == hit->crate_id) && (slot == hit->slot_id) &&
495  (chan == hit->chan_id) && (hit->module_id == F1TDC48) &&
496  (hit->module_mode == mode) )
497  {
498  /* printf("f1tdc48_write_data: DEBUG: found hit for crate %d"
499  * " slot %d chan %d.\n",roc,slot,chan);
500  */
501 
502  chit[jj] = hit;
503  jj++;
504  if (jj >= F1TDC48_MAX_HITS) {
505  printf("f1tdc48_write_data: ERROR: Too many hits for channel\n");
506  jj--;
507  break;
508  }
509  }
510  }
511  /* printf("write hit data %d\n",jj); */
512  for (ii=0; ii < jj; ii++) {
513  F1TDC48_F1_DATA(cdata,chip,chan_on_chip,chit[ii]->hdata[0]);
514  }
515 
516  /* Check for outputing chip trailer */
517 #if 0
518  if (chan == 47) {
519  F1TDC48_F1_TRAILER(cdata,(eventNum&0x3f),(ts&0x1ff),chan);
520  }
521 #endif
522 
523  }
524 
525  nwords = dabufp - start;
526  if ((nwords%2) == 0) {
527  F1TDC48_FILLER(slot);
528  nwords += 2;
529  F1TDC48_BL_TRAILER(slot,nwords);
530  } else {
531  nwords += 1;
532  F1TDC48_BL_TRAILER(slot,nwords);
533  }
534 
535  if (nwords%4 != 0) {
536  F1TDC48_FILLER(slot);
537  F1TDC48_FILLER(slot);
538  nwords += 2;
539  }
540 
541  return nwords;
542 }
543 
544 
545 /* CAEN 1290 Hi Res TDC Parameters */
546 #define CAEN1290_MAX_CHAN 32
547 #define CAEN1290_MAX_HITS 8
548 #define CAEN1290_MAX_CHIPS 4
549 
550 
551 /* CAEN 1290 TDC Macros */
552 #define CAEN1290_BL_HEADER(slot,evt) {*dabufp++ = 0x40000000 | (evt << 5) | (slot); }
553 #define CAEN1290_BL_TRAILER(slot,nwords,status) {*dabufp++ = 0x80000000 | ((status&0x7) << 24) | (nwords << 5) | (slot); }
554 
555 #define CAEN1290_TDC_HEADER(chip,evt,bid) {*dabufp++ = 0x08000000 | ((chip&0x3) << 24) | ((evt&0xfff) << 12) | (bid&0xfff); }
556 #define CAEN1290_TDC_DATA(edge,chan,time) {*dabufp++ = 0x00000000 | ((edge&1) << 26) | ((chan&0x1f) << 21) | (time&0x1fffff); }
557 #define CAEN1290_TDC_TRAILER(chip,evt,nwords) {*dabufp++ = 0x18000000 | ((chip&0x3) << 24) | ((evt&0xfff) << 12) | (nwords&0xfff); }
558 
559 #define CAEN1290_TDC_ERROR(chip,eflags) { *dabufp++ = 0x20000000 | ((chip&0x3) << 24) | (eflags&0x7fff); }
560 
561 #define CAEN1290_FILLER {*dabufp++ = 0xC0000000; }
562 
563 
564 int
565 caen1290_write_data (CODA_EVENT_INFO *event, int roc, int slot, int mode)
566 {
567  int ii, jj, chan, hcnt, nwords=0, wcnt=0;
568  //uint64_t tsdiv;
569  uint32_t chip, stat, edge = 0;
570  uint32_t eventNum;
571  // uint64_t timestamp;
572  unsigned int *start = dabufp;
573  CODA_HIT_INFO *hit;
574  CODA_HIT_INFO *chit[MAX_HITS_PER_CHAN];
575 
576  eventNum = (event->eventid)&0xffffffff;
577  // timestamp = (event->trigtime);
578  hcnt = event->hcount[(roc-1)][(slot-1)];
579 
580 
581  /* Set Status to 0 for now */
582  stat = 0;
583 
584 
585  CAEN1290_BL_HEADER(slot,eventNum);
586 
587  /* printf("caen1290_write_data: %d hits checking slot %d"
588  * " roc %d.\n",hcnt, slot, roc);
589  */
590 
591  /* Loop over all channels */
592  chip = 0;
593  for (chan=0; chan < CAEN1290_MAX_CHAN; chan++) {
594 
595  /* Check for outputing Chip Header */
596  if ((chan%8) == 0) {
597  CAEN1290_TDC_HEADER(chip, eventNum, 0);
598  wcnt=0;
599  chip++;
600  }
601 
602  /* check for all hits for this channel */
603  jj=0;
604  for (ii=0; ii < hcnt; ii++) {
605  hit = (CODA_HIT_INFO *) &event->hits[(roc-1)][(slot-1)][ii];
606  /* printf("%d %d %d %d\n",hit->crate_id,hit->slot_id,
607  * hit->chan_id,hit->module_id);
608  */
609  if ( (roc == hit->crate_id) && (slot == hit->slot_id) &&
610  (chan == hit->chan_id) && (hit->module_id == CAEN1290) &&
611  (hit->module_mode == mode) )
612  {
613  /*printf("caen1290_write_data: DEBUG: found hit for crate %d"
614  * " slot %d chan %d.\n",roc,slot,chan);
615  */
616 
617  chit[jj] = hit;
618  jj++;
619  wcnt++;
620  if (jj >= CAEN1290_MAX_HITS) {
621  printf("caen1290_write_data: ERROR: Too many hits for channel\n");
622  return 0;
623  }
624  }
625  }
626  /* printf("write hit data %d\n",jj); */
627  for (ii=0; ii < jj; ii++) {
628  CAEN1290_TDC_DATA(edge,chan,chit[ii]->hdata[0]);
629  }
630 
631  /* Check for outputing chip trailer */
632  if (((chan+1)%8) == 0) {
633  CAEN1290_TDC_TRAILER(chip, eventNum, wcnt);
634  }
635 
636  }
637 
638  CAEN1290_BL_TRAILER(slot,nwords,stat);
639 
640  nwords = dabufp - start;
641 
642  while ((nwords%4) != 0) {
643  CAEN1290_FILLER;
644  nwords++;
645  }
646 
647  return nwords;
648 }
649 
650 
651 #define MAX_CONFIG_PARS 20
652 
653 void WriteDAQconfigBank(CODA_CRATE_MAP *crate, int roc)
654 {
655 
656  // Get type of digitization modules in this crate. Assume all are the same
657  enum type_id_t modtype = UNKNOWN;
658  int i;
659  for(i=0; i<MAX_SLOTS; i++){
660  int mymodtype = crate->module_map[i];
661  switch(mymodtype){
662  case FADC250:
663  case FADC125:
664  case F1TDC32:
665  case F1TDC48:
666  case CAEN1190:
667  case CAEN1290:
668  modtype = mymodtype;
669  break;
670  default:
671  break;
672  }
673  if(modtype != UNKNOWN) break;
674 
675  if(mymodtype>TID && mymodtype<TD){
676  modtype = crate->module_map[i];
677  break;
678  }
679  }
680 
681  // Write parameters based on module type
682  uint32_t Npar = 0;
683  uint32_t partype[MAX_CONFIG_PARS];
684  uint32_t parvalue[MAX_CONFIG_PARS];
685  switch(modtype){
686  case FADC250:
687  partype[Npar] = kPARAM250_NSA_NSB; parvalue[Npar++] = FADC250_WINDOW_WIDTH;
688  //partype[Npar] = kPARAM250_NPED; parvalue[Npar++] = 4; // hardwired in 1st gen. firmware
689  partype[Npar] = kPARAM250_NPED; parvalue[Npar++] = 1; // we save only one pedestal channel
690  break;
691  case FADC125:
692  partype[Npar] = kPARAM125_NSA_NSB; parvalue[Npar++] = FADC125_WINDOW_WIDTH;
693  partype[Npar] = kPARAM125_WINWIDTH; parvalue[Npar++] = FADC125_WINDOW_WIDTH; // this is currently unused in offline code?
694  //partype[Npar] = kPARAM125_NPED; parvalue[Npar++] = 4; // hardwired in 1st gen. firmware
695  partype[Npar] = kPARAM125_NPED; parvalue[Npar++] = 1; // we save only one pedestal channel
696  break;
697  case F1TDC32:
698  case F1TDC48:
699  partype[Npar] = kPARAMF1_REFCNT; parvalue[Npar++] = 0; // Need to get a real number here
700  partype[Npar] = kPARAMF1_HSDIV; parvalue[Npar++] = 0; // Need to get a real number here
701  break;
702  case CAEN1290:
703  partype[Npar] = kPARAMCAEN1290_WINOFFSET; parvalue[Npar++] = 0; // This is just a placeholder
704  default:
705  break;
706  }
707 
708  // If no parameters to write, then don't write bank at all
709  if(Npar == 0) return;
710 
711  // Open data bank of type DAQConfig=0x55
712  DATA_BANK_OPEN(0,0x55,1);
713 
714  // write header word
715  uint32_t slot_mask = crate->moduleMask;
716  *dabufp++ = (Npar<<24) | slot_mask;
717 
718  // Write all parameters
719  uint32_t ii;
720  for(ii=0; ii<Npar; ii++){
721  *dabufp++ = (partype[ii]<<16) | (parvalue[ii]);
722  }
723 
724  // Close data bank (see note above regarding DATA_BANK_CLOSE)
725  DATA_BANK_CLOSE;
726 }
727 
728 
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