FASTBUS READOUT CONTROLLER (FRC)
The FASTBUS Readout Controller (FRC) is a single width FASTBUS resident CPU, whose task is to read data from FASTBUS modules in its FASTBUS crate and store that data in its internal memory. A trigger signal (or a FASTBUS broadcast message) interrupts the CPU. This causes the CPU to execute code that reads out the FASTBUS modules. The CPU is assisted by onboard DMA logic in the readout process. The CPU control allows very flexible methods of readout. The FRC can store and manage a number of data buffers.
The data stored in the FRC's memory is available to any FASTBUS master or to any other device that can access the FRC through the auxilliary port. The FRC implements a specific, but simple protocol on the auxiliary port. In the Collider Detector Facility (CDF) Data Acquisition system, the auxilliary port is used by a VSB master (Scanner) to read data from the FRC's memory at a rate > 20 MB/s. Onboard DMA logic eases the burden on the CPU. The trigger signal is received on an "Interface to equipment" card. The memory implementation of the FRC allows simultaneous memory accesses by the CPU, FASTBUS and FASTBUS Auxilliary connector.
The major functional elements of the FRC are: The RISC Controller, Memory System, FASTBUS Master/Slave Interface, The Auxilliary Card Interface and Interface to the experiment thru front panel 80 pin I/O port connector.
The LR33000 RISC Controller contains 8 KB of Instruction Cache, 1 KB of Data Cache, a DRAM controller and counter/timers
on chip. Both caches are directly mapped. The DRAM controller supports a variety of DRAM configurations including
page mode DRAMs. A full description of the controller is available from LSI Logic Corporation's LR33000 MIPS Embedded
Processor User's Manual.
The main memory of the FRC consists of 8 256K x 4 Triple Port Video DRAMs, organized as 4 banks of 256K x 32 bit wide dynamic memory. All memory is byte, halfword and word addressable. The fast page mode dynamic RAM port of the Triple Port DRAM (TPDRAM) is dedicated to the LR33000, Serial Access Memory Port 'b' (SAMb port) is dedicated to the FASTBUS Interface and the Serial Access Memory Port 'a' (SAMa port) is dedicated to the Auxilliary Card Interface. The main memory contains FASTBUS execution list programs. The size of the main memory permits data from many events to be buffered. The memory system with the triple port DRAM, is very efficient for sequential transfer operations both on the FASTBUS side and the Auxiliary side.
The dynamic part of the main memory refreshes are accomplished by the DRAM controller of the LR33000 or logic inside one of the FPGA's. The serial part of the main memory requires no refreshing. The DRAM is accessible at physical or virtual address 0000 0000 - 003F FFFC in user mode and 8000 0000 - 803F FFFC virtual (0000 0000 - 000F FFFC physical) address in kernel mode. The CPU enters kernel mode after an exception. Restore from exception instruction puts it in user mode.
The FRC contains 2 MB maximum of 32-bit wide PROM memory, which may be used to hold start up and diagnostic
code. The PROM is accessible starting at virtual address BFC0 0000.
2M Bytes of video RAM & 2MB EPROM
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+5.0 Volts |
6 Amps |
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-5.2 Volts |
2 Amps |
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-2.0 Volts |
0.2 Amps |
3 lbs.