Global Trigger

The Global Level 1 Trigger is responsible for establishing the first ``rough cut'' on incident photon energy using only prompt information from individual detector subsystems. Ideally it should run ``deadtimeless'' by continually updating state changes in the detector. It must run as fast as possible as this time determines the pipeline length for the front-ends. Output to the front-ends is basically a time index into their data buffers.

With the current detector design the primary candidates for input to the trigger include: energy in the Forward Calorimeter, energy in the Barrel Calorimeter (preferrably segmented in theta), track counts in the Forward Time of Flight, Barrel Calorimeter, and ``start counter''. Trigger definitions would include: Min/Max/Exact numbers of tracks, Min/Max total energy deposited, time windows for mtching detector subsystems, and an output delay from a trigger ``match''.

The Global Trigger Processor (GTP) is shown as a schematic diagram in Figure 1. It consists of five separate subsystems located at or near the front-end. Each subsystem computes continuously at the pipeline rate of the digitization (e.g. 250 $\,$ MHz ). Eash subsystem ``timestamps'' its output based on a synched distributed master clock (10 bits at 250 $\,$ MHz would provide a 4 $\mu$ s window before rollover). The output for each subsystem would be in the format of a Subsystem Event Report (SER - might look like <Hdr:6><Time:10><Func1:8><Func2:8> ) and would be sent via a fast (greater than GB/s) optical link to the main GTP. Output need only be sent to the GTP if there were changes to report from a particular subsystem.

The GTP would run at the same synched distributed clock speed as the subsystems. It would receive and buffer the SERs from each subsystem and use multiple internal processors to find a match for one of many triggers (8-16 types). Output of a valid Level 1 trigger should be programmably delayed to the front-end electronics. This simplifies the front-end readout in that it becomes a fixed lookback into the pipeline.

**Figure 1:** Global Level 1 Trigger
Flight/Detector Time	30 ns
PMT Latency	30 ns
Cables to FEE	30 ns
FEE to trigger out	64 ns
Subsystem Processing	200 ns
Transfer SER to GTP	100 ns
GTP Processing	400 ns
Level 1 output to FEE	50 ns

The total time is less than 1 $\mu$ s. If the front-end electronics are designed for a pipeline of 1.536 $\mu$ s (384 stages at 250 $\,$ MHz ) this would probably be sufficient.