2009-08-10 16:21:35

F1 TDC

For Normal Resolution and Synchronous mode, we need to change only Registers 7, 8, 9, and 10 and we can use the default configurations as follows:


Register  0 : 0180
Register  1 : 0000
Register  2 : 4040
Register  3 : 4040
Register  4 : 4040
Register  5 : 4040
Register  6 : 0000
Register  7 : C880
Register  8 : 63A4
Register  9 : CDEC
Register 10 : 1FBC
Register 11 : 0000
Register 12 : 0000
Register 13 : 0000
Register 14 : 0000
Register 15 : 000C


  • Register 7 bits 6-14 : Interval (tframe) between start signals (refcnt : reference starter counter)
 
   tframe = ( refcnt + 2 ) * Tref
   refcnt = tframe / Tref - 2

  • Register 8  : Trigger window width (trigwin)
   
trigwin < 0.9 * tframe

  • Register 9 : Trigger window latency or offset (triglat)
  
 triglat < 0.4 * tframe

  • Register 10 : Resolution (bin size) of the F1TDC by setting the reference clock divider(refclkdiv) and the high speed divider(hsdiv)
   
   # bits 8-10 : refclkdiv (possible factor 1,2,4,...128) 2refclkdiv
   # bits 0- 7 : hsdiv, 0 - 255

Thus, resolution is

 
Resolution  = Tref * 2refclkdiv / (152*hsdiv), where Tref = 25 ns (by clock 40 MHz)  


Ordering
  • decide the resolution (bin size)
 resolution [ns] = 25  * 2refclkdiv / (152*hsdiv) >>> Register 10 bits 0-10
  • decide the tframe
 tframe = ( refcnt + 2 ) * 25
 refcnt = tframe / 25 - 2 >>>  Register 7 bits 6-14 
  • decide the window width (ns)
  window [ns] = trigwin * resolution 
  trigwin = window / resolution  < 0.9 * tframe >>> Register 8 
  • decide the latency (ns)
 latency [ns] = triglat * resolution 
 triglat = latency / resolution < 0.4 * fframe >>> Register 9 
  • Using resolution, we can calculate "full_range"
 full_range = 65536 * resolution 
Acronyms
  • Tref : 25 ns (40 MHz Reference Internal Clock)
  • refcnt : Reference Start Counter (Register 7 bits 6-14)
  • tframe : Start interval or restart period (interval between start signals)
  • refclkdiv : Reference Clock Divider (Register 10 bits 8-10)
  • hsdiv : High Speed Divider (Register 10 bits 0-7)
  • trigwin : Trigger Window
  • triglat : Trigger Window Latency or Offset
For a draft log file, F1 TDC configuration log txt file

Posted by Jeong Han Lee | Permanent link