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EECAD

Recreate a Viewlogic Schematic File and Convert the Accompanying PCAD files

  1. In the PCAD Library management module, create a .plb file containing your .prt files.
  2. In the PCAD PCB module, translate the plb file using the PDIF writer. Select the the Indented option and set the Scan Reserved Characters option before you create the file.
  3. Open Accel Library Manager. Go to the Library pull down and select translate. For the Source file format, select PDIF. Click on the Source Library button and select .pdf file. Click on the Destination Library button and enter a name for your new library. If you used a PCAD cross reference file to define power and hetrogeneous gate information, then you will need to click on the PDIF Cross Reference button and select the file. (If you defined your power using the PWGD attribute on the gate and if you have only homogeneous components, you do not need to worry about a cross refence file.) Click on the Translate button at the bottom. Next you will get a dialog box asking about layer mapping. Unless you used some custom layers, you can click on the OK button to accept the default. Translating will continue and you will be given the option to view the log file at the end. I would recommend doing this and maybe even printing it out if you have a lot of errors. When you translate your .plb, it is possible that you will get a warning that looks like: Warning: The number of components pins created for AD637 does not match the number of PIN_DEF entries near line 176. Power pins might be missing. This is Accel flagging something that it thinks is a problem and most likely it's not.
  4. Create or copy in the symbols needed to complete the components you created from your PCAD library. Now open each component, add the necessary symbol(s) and verify gate information, pin count and your pin table.
  5. Open the Accel EDA PCB editor, and got to Library setup. Clear what's there and set it to your library file. Now, open your PCAD PCB file. Select Embedded Aperature Tabe in the Convert Pad Definitions box. (This will create padsytles for your through hole components that are all defined as 60 mil round with a 38 mil hole. If you select Create from Pad graphics, unless you have created absolutely dead on pad graphics, you will get odd size padstyles. Selecting the Embedded Aperature option tends to be a lot less clean up.) If you specified a PCAD Cross reference file in step three above, you will need to do it here also. Click OK to continue reading in your file. Once complete, view & print out your log file and correct any real errors there.
  6. Open up one of the format files and cut & paste your PCB into it. Save your file as a new name and close the old PCB file without saving it.
  7. Clean up the PCB file by doing the following: Delete all the component names from the Silkscreen and Top Assembly layers; Fix the padstyle definitions; Verify font style for reference designators; Update drawing format to contain the same information contained on the existing drawings(fab and assembly). The fab drawing can be quite helpful while fixing the padstyles as it contains the hole size information. If there are numerous unfilled copper pour areas on the top and bottom layers, review them to see what net they are assigned to and if they are all part of the same net, such as ground, create one large copper pour that encompasses the area occupied by the smaller pours. Delete the numerous smaller pours and the straps that are there. Assign the copper pour to the the appropriate net and pour it. Verify that it is as it should be by comparing it to the hard copy of that layer.
  8. Open the Schematic editor and open a drawing setup. Set your library to the same library you were using in PCB. Begin laying out your schematic. You will need to either keep your PCB editor open while you do this or generate and print a netlist file for your PCB. The reason for this is that as you layout your schematic, you will need to rename your nets as you make your connections so that they will match the PCB file.
  9. Once your schematic is complete, generate a netlist from it. Go into your PCB editor and run a Compare between the two netlists. Fix any errors or warnings that you can and continue this process until the two match with no errors and no warnings (if possible).